1. Field of the Invention
This invention relates to data memories with sense amplifiers.
2. Description of the Prior Art
Many random access memories (RAMs) employ sense amplifiers to increase the speed of reading data stored in respective memory cells. In typical RAMs the memory cells are arranged in groups (or rows), with each sense amplifier being connected in parallel to a respective memory cell in each of the rows. A part of a memory address supplied to the RAM is used to select and activate one of the rows; the outputs of the memory cells in the activated row are connected via bit lines to the inputs of the sense amplifiers.
A RAM read or write cycle may be initiated either by placing a new address on an address input of the RAM (which is usually the case for individual RAM chips) of by a transition in a clock or other control signal (which is generally the case for a RAM in an embedded controller device). A number of events then take place. Firstly, a state of RAM pre-charge is disabled, releasing the RAM from an idle condition and priming it for an active read of write operation. At the same time, of very shortly after, a row decoder starts to decode the input address, in order to generate a unique row-line output. For a medium sized RAM this may involve decoding eight address inputs to select one of 256 row control lines. After the row control line has been selected, all of the memory cells which are controlled by that row control line are activated, and those particular memory cells can be read-from or written-to.
In the case of a read cycle, the selected memory cells begin to charge or discharge bit lines connecting the memory cells to the respective sense amplifiers, and subsequently the charge currents or resulting voltage changes on the bit lines are detected by the sense amplifiers. Each memory cell is physically small and so the drive strength is weak, yet the bit lines are shared by many memory cells. Inevitably, the rate of voltage of current change on the bit lines is slow, and so high-gain sense amplifiers are used for high-speed RAMs because they can react quickly to small changes in input. Finally the outputs of the sense amplifiers (i.e. the data output of that row of the RAM) are written to the system of output data bus via a powerful buffer.
Between the bit-lines and the sense amplifier there may also be a multiplexing stage (column decode) which further reduces the selection of RAM cells before presentation at the sense amplifier inputs, though this stage is often absent; column decoding is often enabled at the same time as row decoding.
Sense amplifiers are designed to be most responsive when their input or inputs are in the RAM-idle state. In this way the sense amplifiers are primed and ready to react quickly to any change in input current or voltage. The idle state of a memory cell often means that the sense amplifier's inputs are pre-charged to a logic-high level, or equalised to a mid-range level. While the sense amplifier inputs are in this primed mode, the sense amplifier consumes maximum current. The sense amplifier's current drain (and power consumption) will not begin to diminish until sensing takes place, and this needs a movement in the input current or voltage.